Hazard-Free Implementation of the Self-Timed Cell Set in a Xilinx FPGA

When designing asynchronous systems, the problems of hazards becomes an important issue. This paper deals with the hazard-free implementation of asynchronous logic in a look-up table based FPGA. First, the definitions of hazards and techniques to deal with them in gate-level asynchronous circuits are surveyed. Then the look-up table (LUT) model and its associated timing properties are presented. Finally, a list of line delay constraints for a hazard-free implementation of the self-timed modules is presented and the conditions under which the cell set is hazard-free is explained. Our technique is illustrated in the implementation of the basic asynchronous macromodules outlined in Sutherland[16], Ebergen[8] and Brunvand[6]) using the Xilinx 4000 Series FPGA.